OK, I didn't try current -mm, however I managed to nail it down completely.
This is the culprit inside 2.6.10-mingoll.diff:

Index: linux-2.6.10-ckdev/arch/i386/kernel/cpu/mtrr/generic.c
===================================================================
--- linux-2.6.10-ckdev.orig/arch/i386/kernel/cpu/mtrr/generic.c	2004-12-30 10:04:29.000000000 +1100
+++ linux-2.6.10-ckdev/arch/i386/kernel/cpu/mtrr/generic.c	2004-12-30 14:31:16.559914088 +1100
@@ -240,14 +240,11 @@
 	/*  Note that this is not ideal, since the cache is only flushed/disabled
 	   for this CPU while the MTRRs are changed, but changing this requires
 	   more invasive changes to the way the kernel boots  */
-	/*
-	 * Since we are disabling the cache dont allow any interrupts - they
-	 * would run extremely slow and would only increase the pain:
-	 */
-	spin_lock_irq(&set_atomicity_lock);
+	spin_lock(&set_atomicity_lock);
 
 	/*  Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
 	cr0 = read_cr0() | 0x40000000;	/* set CD flag */
+	wbinvd();
 	write_cr0(cr0);
 	wbinvd();
 
@@ -269,7 +266,8 @@
 
 static void post_set(void)
 {
-	/*  Flush TLBs (no need to flush caches - they are disabled)  */
+	/*  Flush caches and TLBs  */
+	wbinvd();
 	__flush_tlb();
 
 	/* Intel (P6) standard MTRRs */
@@ -281,7 +279,7 @@
 	/*  Restore value of CR4  */
 	if ( cpu_has_pge )
 		write_cr4(cr4);
-	spin_unlock_irq(&set_atomicity_lock);
+	spin_unlock(&set_atomicity_lock);
 }
 
 static void generic_set_all(void)