From 5674b1518fcfce5317f28319c0f919ab18681751 Mon Sep 17 00:00:00 2001 From: Con Kolivas Date: Sat, 22 Oct 2016 09:43:58 +1100 Subject: [PATCH 86/89] Make the cpu_idle_map cacheline aligned. --- kernel/sched/MuQSS.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/sched/MuQSS.c b/kernel/sched/MuQSS.c index a921794..b71b237 100644 --- a/kernel/sched/MuQSS.c +++ b/kernel/sched/MuQSS.c @@ -162,8 +162,6 @@ int sched_iso_cpu __read_mostly = 70; */ static int prio_ratios[NICE_WIDTH] __read_mostly; -static cpumask_t cpu_idle_map; - /* * The quota handed out to tasks of all priority levels when refilling their * time_slice. @@ -174,6 +172,8 @@ static inline int timeslice(void) } #ifdef CONFIG_SMP +static cpumask_t cpu_idle_map ____cacheline_aligned_in_smp; + /* * We add the notion of a root-domain which will be used to define per-domain * variables. Each exclusive cpuset essentially defines an island domain by -- 2.7.4